module led_state_change(
	input clk_10Hz,
	input rst_n,
	output reg[7:0] led_state
);

	always @(posedge clk_10Hz or negedge rst_n) begin
		
		if(rst_n == 1'b0) begin
			led_state <= 8'b0000_0001;
		end
		else begin
			if(led_state == 8'b1000_0000) begin
				led_state <= 8'b0000_0001;
			end
			else begin
				led_state <= led_state << 1;
			end
		end
		
	end

endmodule
